1. Field of the Invention
The invention relates to asymmetrical multiprocessor computer systems and more particularly to such computer systems where one processor is a system language processor and another processor is a system control processor.
2. Prior Art
Asymmetrical multiprocessor computer systems are known but not where the main storage or system language processor is connected to run under control of a system control processor and runs until it encounters a predefined condition which causes interruption of the system control processor. The system control processor then handles the condition causing the interrupt and restarts the system language processor.